(1) Field of the Invention
This invention relates to a method of fabricating multilevel interconnected vertical channels and horizontal channels or tunnels, for applications in both integrated circuits and bio-sensors, forming copper interconnects and inductors by atomic layer deposition, ALD, of a copper barrier layer and copper seed layer, in the vertical channels and horizontal channels or tunnels.
(2) Description of Related Art
In this section a description of related Prior Art background patents follows.
U.S. Pat. No. 6,225,221 B1 entitled xe2x80x9cMethod to Deposit a Copper Seed Layer for Dual Damascene Interconnectsxe2x80x9d granted May 1, 2001 to Ho et al. describes a method of depositing a copper seed layer in the manufacture of an integrated circuit device. The copper seed layer is thin and conformal for subsequent electroless plating of copper. A dielectric layer is patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer of tantalum, titanium, or tungsten is deposited overlying the dielectric layer to line the vias and trenches. A copper seed layer is deposited overlying the barrier layer by the reaction of CuF2 vapor with the barrier layer.
U.S. Pat. No. 6,284,646 B1 entitled xe2x80x9cMethod of Forming Smooth Conductive Layers for Integrated Circuit Devicesxe2x80x9d granted Sep. 4, 2001 to Leem describes a method for forming a metal layer for an integrated circuit device includes forming a first conductive layer on an integrated circuit substrate. While forming the first conductive layer, a reflection index of the first conductive layer is monitored, and the formation of the first conductive layer is terminated when the reflection index of the first conductive layer reaches a predetermined value. The first conductive layer can be an aluminum layer having a thickness in the range of approximately 500 Angstroms to 1500 Angstroms.
U.S. Pat. No. 6,249,039 B1entitled xe2x80x9cIntegrated Inductive Components and Method of Fabricating Such Componentsxe2x80x9d granted Jun. 19, 2001 to Harvey et al. teaches a method of fabricating inductive components in which there is built up thin films in trenches. An inductive component includes a substrate on the surface of which is a lower insulation layer having a shallow concavity or trench, a first plurality of conductive elements formed in the trench, a magnetic core formed over the first plurality of conductive elements, and a second plurality of conductive elements formed over the core. The first and second pluralities of conductive elements are connected to each other so as to form an inductive coil around the core. First and second core insulation layers are disposed between the core and the first and second pluralities of conductive elements, respectively. The component is fabricated by a method in which it is built up in the trench using thin film techniques.
U.S. Pat. No. 6,187,647 B1 entitled xe2x80x9cMethod of Manufacturing Lateral High-Q Inductor for Semiconductor Devicesxe2x80x9d granted Feb. 13, 2001 to Chu teaches a method of forming an inductor for a semiconductor device comprises the steps of forming the bottom legs on a first substrate; depositing a second substrate layer over the first substrate; forming the pair of side legs for each loop through the second substrate layer; and, forming top legs connecting pairs of side legs extending from adjacent bottom legs. The step of providing the side legs includes forming a pair of vias through the second substrate layer to the bottom legs, and depositing side legs in the vias. The step of forming the top legs preferably includes forming a channel between the pairs of vias respectively communicating with the adjacent bottom legs, and depositing top legs in the channels. Additionally, the steps of forming the side and top legs are performed concurrently.
U.S. Pat. No. 6,305,314 B1 entitled xe2x80x9cApparatus and Concept for Minimizing Parasitic Chemical Vapor Deposition During Atomic Layer Depositionxe2x80x9d granted Oct. 23, 2001 to Sneh et al. teaches a method and apparatus for avoiding contamination of films deposited in layered depositions, such as Atomic Layer Deposition (ALD) and other sequential chemical vapor deposition (CVD) processes. The CVD deposited contamination of ALD films is prevented by use of a pre-reaction chamber that effectively causes otherwise-contaminating gaseous constituents to deposit on wall elements of gas-delivery apparatus prior to entering the ALD chamber.
It is a general object of the present invention to provide an improved method of forming multilevel interconnected vertical channels and horizontal channels or tunnels. The method has broad applications in both integrated circuits and bio-sensors: in the field of semiconductors, for fabricating both copper interconnects and inductors, and in the field of bio-sensors, for applications in the formation of mini- or micro-columns for gas or liquid separation, and gas/liquid chromatography, and similar capillary separation techniques. Furthermore, for semiconductor integrated circuit applications, special techniques are described to deposit by atomic layer deposition, ALD, a copper barrier layer and seed layer, for subsequent electroless copper plating, filling trench and channel or tunnel openings, in a type of damascene process to form copper interconnects and inductors.
A process flow outlining the method of the present invention is as follows, for interconnects and inductors:
(1) Formation of trenches and channels by using a sacrificial silicon nitride layer
(2) Atomic layer deposition of a copper barrier layer and copper seed layer in the trenches and channel,
(3) Electroless deposition of copper upon seed layer,
(4) Chemical mechanical polishing back of excess copper,
(5) Barrier deposition, SiN, to seal the copper openings in forming copper interconnects and inductors.
Key to the method of the present invention, is the use of a sacrificial silicon nitride layer to form trenches and channels. Also, key is the deposition by atomic layer deposition of a copper barrier layer and copper seed layer, for subsequent electroless copper plating in a damascene type process, with trench and channel or tunnel openings. The end result is the fabrication of inlaid copper interconnects and inductors.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTSxe2x80x9d section.